Here's the link from Rambus' website:
This is how we know it's important thanks to sabatino:
<<To address these challenges, Rambus has been building a patent portfolio for mobile memory with several proprietary technologies in the Mobile XDR (extreme-data-rate) memory architecture (Figure 3). For example, the company’s low-swing differential-signaling technique delivers high data-rate performance at low voltage. Rambus has heavily invested in JEDEC’s LPDDR2/3 standards, which use single-ended signaling, in which data and command/address signals are referenced to ground.>>
This is where it came from:
<<The other new technique--near ground signaling—was applied in a differential version in an ISSCC paper in February 2007. The new version uses single-ended signaling. It opens the door to use of power sources as low as 0.5V and 80 percent reductions in signaling I/O thanks to very low voltage swings.
This was from 2007:
<< "This test chip is amazingly good, and we are all very happy about that," said chief scientist Mark Horowitz, a Rambus founder who was one of the paper's co-authors. "For many papers you have to stand on your tippy-toes and pray to the demo gods that it will be just so. That's not the case here. There are some robustness and volume-manufacturing issues, but nothing that concerns me." Horowitz is also a professor ofcomputer science and electrical engineering at Stanford University.
Indeed, the technology may represent a more mainstream opportunity than the high-end, speed-driven interconnects for which Rambus is usually known.
"This is intended for high-volume computer and consumer applications," said Kevin Donnelly, senior vice president of engineering at Rambus. A separate project in the works at Rambus aims to hit the same 2.2-mW/Gbit/s power level but will deliver as much as four times the performance using 65-nm technology. "The power budget for the next generation has to be the same as the old power budget," said Donnelly.>>
How Rambus did it:
<<The Rambus work used a combination of techniques to achieve its 2.2-mW/Gbit/s milestone, including a voltage-mode signaling technique developed by UCLA researcher Ken Yang. "There isn't any one thing you can do to reduce the overall power," said Horowitz. "You need innovations in logic, clocking, signaling, as well as in the basic transmitter and receiver. We had some synergies in some areas and in others we just had to be clever."
Two big areas of innovation were in shifting the focus of adaptive equalization from the transmitter to the receiver and driving more of the equalization work from dedicated hardware to software on a basic microcontroller. "If you start at the far end of the receiver and work your way back after you deliver a receiver that is as sensitive as possible, you get a cycle of goodness in power savings all across the system," said co-author John Poulton, a computer science professor at the University of North Carolina at Chapel Hill.
Researchers found a way to use existing information from a clock-data recovery (CDR) unit to measure the loss of high frequencies in the signal and compensate by effectively turning up what Dally called "a treble knob" in the receiver.
CDR data on when the system clock is early and late "gives you exactly what you need to know about whether the [signal] eye is closed or open," said lead author Robert Palmer, who will present the ISSCC paper. Having that data, along with some clever use of other existing blocks, eliminates the need for oscillator and interpolator logic used in typical receivers.
"There was no extra hardware to handle the adaptive equalization," said Palmer. "In a typical design, the interpolation logic uses as much power as our whole link," said Dally. The resulting sensitivity of the receiver allowed engineers to eliminate signal pre-emphasis and multitap equalization with hardware FIR filters typically employed at the transmitter stage for high-speed serdes."It takes a lot of energy to use precompensation," said Horowitz. "Many people will be surprised at how aggressive we have been in pushing more functions from logic into software."